The present invention relates to an impedance calibration method of a driver and on-die termination (hereinafter referred to as “ODT”) of a synchronous memory device, and more particularly, to an improved driver and ODT impedance calibration method of a synchronous memory device in which the calibration is normally made in an enable state to match a present impedance situation with a compensation for this.
In general, a semiconductor device such as a memory device exchanges data and the like with an external system. However, if the bus-line impedance used to connect a semiconductor device and an external system is different from the signal-line impedance of the semiconductor device directly connected to the bus line, it may cause a reflection of the data. In recent high-speed semiconductor devices, an impedance-matching device, such as an ODT device, is provided to prevent such a data reflection.
The ODT device includes resistance elements and is connected to an input/output line, which is connected to the input/output pad of the semiconductor device. The ODT device selectively turns on/off the resistance elements connected to the input/output line, thereby calibrating the impedance of the input/output line.
FIG. 1 is a circuit diagram showing an example of a device that calibrates the impedance of an ODT device.
In FIG. 1, an internal calibration enable signal (int_calen), a signal generated in the ODT impedance calibration mode, is generated inside the semiconductor device.
An external calibration enable signal (ext_calen) is a signal which is applied from outside during normal operation of the semiconductor device. The external calibration enable signal (ext_calen) is a signal to be applied in calibrating the ODT device impedance when a characteristic of the semiconductor device is changed due to the variation of temperature, voltage, and the like during normal operation.
In FIG. 1, an oscillator 110 receives an internal calibration enable signal (int_calen) at high level to output an oscillation signal (osc_clk). An M-bit counter 11 counts the pulse number of the oscillation signal (osc_clk).
A maximum counter trigger signal generator 120 is controlled by the M-bit counter 11, and, when the pulse of the oscillation signal (osc_clk) is M-th, the maximum counter trigger signal generator 120 transmits a trigger signal (int_discal) from low level to high level.
A pulse generator (130) is synchronized with the rising edge of the oscillation signal (osc_clk) to output a pulse signal (G_calp). Moreover, the pulse generator 130 receives the trigger signal (int_discal) and external calibration enable signal (ext_calen).
An oscillator 140 receives the pulse signal (G_calp) generated by the pulse generator 130, and controls the operation of the pulse generator 150. Here, a pulse signal (L_calp) outputted from the pulse generator 150 is synchronized with the rising edge of the pulse signal (G_calp) to produce a plurality of pulses.
An N-bit counter 12 counts the pulse number of the pulse generator 150.
A maximum counter trigger signal generator 160 is controlled by the N-bit counter 12, and the maximum counter trigger signal generator 160 disables the operation of the oscillator 140 when the pulse of the pulse signal (L_calp) is N-th.
The ODT impedance calibration portion 170 receives the output signal (L_calp) of the pulse generator 150 to output a plurality of control signals (code<0:n-1>). The ODT impedance is calibrated by the control signal (code<0:n-1>), which is selectively enabled (refer to reference numeral 220 of FIG. 2).
FIG. 2 is a more detailed view showing a portion of the circuit block illustrated in FIG. 1.
As illustrated in FIG. 2, the ODT impedance calibration device 170 includes a comparator 210, an ODT block 220, and an N-bit counter 230.
The comparator 210 and N-bit counter 230 are driven by the pulse signal (L_calp) outputted from the pulse generator 150.
The comparator 210 compares a line voltage (ZQ_in) applied to resistance (RQ) with a reference voltage (Vref).
The N-bit counter 230 receives an output signal (Com_out) of the comparator 210 to output a control signal (code<0:n-1>) which controls the ODT block 220.
The ODT block 220 calibrates the turn-on/turn-off of a PMOS transistor with the control signal (code<0:n-1>) to calibrate the impedance voltage of the ZQ line (ZQ_in). Reference characters A, B, C, and D within the ODT block 220 indicate resistance values.
The resistance (RQ) connected to the ZQ line (ZQ_in) is a reference resistance for calibration of the driver and ODT, which is a resistance targeted with respect to the calibration of P_Leg and L_Leg.
Hereinafter, referring to FIGS. 1 and 2, such a driver and ODT impedance calibration method will be described in more detail.
In general, if a semiconductor device wants to perform a normal operation, the driver and ODT impedance of the internal line, which receive the external signal or transmit the internal signal, should be calibrated to an optimum value. The driver and ODT impedance should be optimized in order to prevent the interference or distortion of the input signal.
An initial ODT impedance calibration in the semiconductor device is performed by the internal calibration enable signal (int_calen).
Then, it is necessary for the semiconductor device to recalibrate the driver and ODT impedance by reflecting the variation of temperature, voltage, and the like while performing a normal operation. In this case, the receipt of an external calibration enable signal (ext_calen) is used to recalibrate the impedance. Typically, however, the minimum period of an external calibration enable signal (ext_calen) is determined. This restricts the number of times available to recalibrate the impedance for a limited period of time.
FIG. 3A is another example of a conventional output driver and ODT impedance calibration circuit, in which the output signal (Pcode<0:5>, Ncode<0:5>) of the calibration circuit calibrates the resistance value of the impedance implemented by the memory device's output driver and ODT device.
The calibration circuit of FIG. 3A includes the calibration control signal generator 301, the P_Leg calibration portion 302, an N-Leg calibration portion 304, a final P_Leg 6-bit latch portion 303, and a final N_Leg 6-bit latch portion 305.
FIG. 3B illustrates an example of the input/output line receiving output signal (Pcode<0:5>, Ncode<0:5>) of FIG. 3A to calibrate the impedance of the line (L).
FIG. 4 is an example of the calibration control signal generator 301 illustrated in FIG. 3A, which includes a calibration enable portion 401, a maximum bit counter portion 402, and a calibration oscillation portion 403.
FIG. 5 is an example of the P_Leg calibration portion 302 illustrated in FIG. 3A, which includes an output driver & ODT P_Leg 501, a 2-stage comparator amplifier 502, and an up-down bit counter portion 503.
FIG. 6 is an example of the N_Leg calibration portion 304 illustrated in FIG. 3A, which includes an output driver and ODT N_Leg 601, a 2-stage comparator amplifier 602, and an up-down bit counter portion 603.
FIG. 7 is an illustration explaining the operation of the circuit illustrated in FIGS. 3A-3B and 4 through 6.
As illustrated above, the calibration control signal generator 301 generates enable signals (Cal_en, Cen—1st, Cen—2nd) in response to the pulse signal (Cal_enp). In other words, as seen in FIGS. 4 and 7, the enable signal (Cal_en) is enabled to high level by the pulse signal (Cal_enp). While the enable signal (Cal_en) is enabled, the calibration oscillator 403 generates the enable signals (Cen—1st, Cen—2nd) having waveforms as shown in FIG. 7. The maximum bit counter portion 402 of FIG. 4 counts a toggling number of the enable signal (Cen—2nd) to output a stop signal (STOP) when the toggling number of the enable signal (Cen—2nd) is matched with the maximum counter set in the maximum bit counter portion 402. The enable signal (Cal_en) of the calibration enable portion 401 is disabled to low level by the stop signal (STOP).
Next, FIG. 5 is an example of the P_Leg calibration portion 302 illustrated in FIG. 3A. In FIG. 5, ZQ is connected to the output driver & ODT P_Leg 501 which is a PMOS impedance portion used as an ODT of external resistances (RQ in FIG. 2), data pull-up output drivers, data, address, and command. A voltage level of the ZQ node and a reference voltage (vrefd) at a predetermined level are compared in the 2-stage comparator amplifier 502. When the voltage level of the ZQ node is lower than that of the reference voltage (vrefd), an output signal (up_dnz) of the 2-stage comparator amplifier 502 becomes high level. When the output signal (up_dnz) becomes high level, an output signal value (Pcode_pre<0:5>) of the up-down bit counter portion 503 increases by one step to reduce an impedance of the output driver and ODT impedance.
FIG. 6 is an example of an N-Leg calibration portion 304 illustrated in FIG. 3a. 
In FIG. 6, an output driver & ODT N_Leg 601 is connected to an output of the P_Leg calibration portion 302 of FIG. 5 and a pull-down N-Leg of the driver, which is provided to calibrate the pull-down N_Leg of the driver according to a level of the output driver & ODT P_Leg 501 of FIG. 5. The N-Leg calibration portion 304 of FIG. 6 outputs an internal voltage Vint while calibrating a count value of the signal Nnode_pre<0:5> to compare with a reference voltage Vrefd, and the 2-stage comparator amplifier 602 compares the reference voltage Vrefd with the internal voltage Vint, and the up-down bit counter portion 603 increases or decreases a value of the signal Nnode_pre<0:5> by one step according to a logic level of an output signal (up_dnz) of the 2-stage comparator amplifier 602.
The above-mentioned process is performed until the increase/decrease of the signal (Pcode_pre<0:5>, Ncode_pre<0:5>) is repeated with the same value (for example, 011100->111100->011100, ->111100, . . . ).
Shown in FIG. 7 is a case where an internal calibration operation is performed three times and a value of the signal (Pcode_pre<0:5>) is increased by one step according to each calibration.
In FIG. 7, when the calibration is terminated by a first pulse signal (Cal_enp), a value of the signal (Pcode_pre<0:5>) is “011100.” However, in the prior art, the value “011100” of the calibrated signal (Pcode_pre<0:5>) is reflected in the output driver and ODT device when a second pulse signal (Cal_enp) is applied. In other words, as seen in FIG. 3, the signal (Pcode_pre<0:5>) having the value “011100” is outputted from the final P_Leg 6-bit latch portion 303 in response to the second pulse signal (Cal_enp). Accordingly, the final P_Leg 6-bit latch portion 303 outputs the signal Pcode<0:5> having the value “011100.”
As a result, there is a problem that the variation of temperature, voltage, and the like corresponding to a present calibration period cannot be reflected in the present calibration but reflected in the next calibration.
On the other hand, FIG. 8 is an illustration for explaining input signal waveforms of a 2-stage comparative amplifier of FIG. 5 and its resulting output signal (Pcode_pre<0:5>) values of the up-down bit counter portion 503. For a reference, an example of the 2-stage comparator amplifier 502 is illustrated in FIG. 15.
As seen in FIG. 8, when a level difference between signals (d0, d0z) is greater than a predetermined level, the comparison time is short and the amplification degree is good as illustrated in {circle around (1)} or {circle around (2)} in FIG. 8, but when a level difference between the input signals is very small as illustrated in {circle around (3)}, it takes a longer time until the next stage amplifies the level to the extent that it can be recognized as a low or high level. When a value is latched in such an unstable region {circle around (3)}, the signal (Pcode_pre<0:5>) may not be increased (Case-1) or decreased (Case-2) by one step; or it may occur a case where a totally different value ends up being latched (Case-3). In such a case, there is a problem that an impedance level of the output driver and an impedance level of the ODT device may get out of an optimal tolerance range.